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2/3/4/6inch diameter Silicon Carbide (SiC) Substrate


2 inch diameter Silicon Carbide (SiC) Substrate Specification

GradeProductionResearch GradeDummy Grade
Diameter50.8 mm±0.38 mm
Thickness330 μm±25μm
Wafer OrientationOn axis :<0001>±0.5°for 4H-N/6H-N/4H-SI/6H-SI
Off axis : 4.0°toward(11
2-0) ±0.5° for 4H-N
Micropipe Density≤5 cm-2≤15 cm-2≤50 cm-2
Resistivity4H-N0.015~0.028 Ω·cm
6H-N0.02~0.1 Ω·cm(90%) >1E5 Ω·cm
4/6H-SI>1E5 Ω·cm
Primary Flat{10-10}±5.0°
Primary Flat Length15.9 mm±1.7 mm
Secondary Flat Length8.0 mm±1.7 mm
Secondary Flat OrientationSilicon face up: 90° CW. from Prime flat ±5.0°
Edge exclusion1 mm
TTV/Bow /Warp≤15μm /≤25μm /≤25μm
RoughnessPolish   Ra≤1 nm
CMP    Ra≤0.5 nm

Cracks by high intensity light

NoneNone1 allowed, ≤1 mm

Hex Plates by high intensity light

Cumulative area≤1 %Cumulative area≤1 %Cumulative area≤3 %

Poly type Areas by high intensity light

NoneCumulative area≤2 %Cumulative area≤5%

Scratches by high intensity light

3 scratches to 

1×wafer diameter 

cumulative length

5 scratches to 

1×wafer diameter  

cumulative length

8 scratches to 

1×wafer diameter  

cumulative length

Edge chipNone

3 allowed, ≤0.5 mm each

5 allowed, ≤1 mm each

Contamination by high intensity

light

None


Notes:
* Defects limits apply to entire wafer surface except for the edge exclusion area.
# Defects shall be existed in the edge area, only defect beyond of the prescribed scope could be considered as reject cause. & the scratches should be checked on Si face only.


3 inch diameter Silicon Carbide (SiC) Substrate Specification

GradeProductionResearch GradeDummy Grade
Diameter76.2 mm±0.38 mm
Thickness350 μm±25μm
Wafer OrientationOn axis :<0001>±0.5°°for 4H- SI 
Off axis : 4.0° toward(11
2-0) ±0.5° for 4H-N
Micropipe Density≤5 cm-2≤15 cm-2≤50 cm-2
Resistivity4H-N0.015~0.028 Ω·cm
4H-SI>1E5 Ω·cm(90%) >1E5 Ω·cm
Primary Flat{10-10}±5.0°
Primary Flat Length22.2 mm±3.2 mm
Secondary Flat Length11.2 mm±1.5mm
Secondary Flat OrientationSilicon face up: 90° CW. from Prime flat ±5.0°
Edge exclusion2 mm
TTV/Bow /Warp≤15μm /≤25μm /≤25μm
RoughnessPolish   Ra≤1 nm
CMP   Ra≤0.5 nm
Cracks by high intensity lightNone1 allowed, ≤1 mm1 allowed, ≤2mm

Hex Plates by high intensity light

Cumulative area≤1 %Cumulative area≤1 %Cumulative area≤3 %

Poly type Areas by high intensity light

NoneCumulative area≤2 %Cumulative area≤5%

Scratches by high intensity light

3 scratches to 

1×wafer diameter 

cumulative length

5 scratches to 

1×wafer diameter 

 cumulative length

8 scratches to 

2×wafer diameter  

cumulative length

Edge chipNone

3 allowed, ≤0.5 mm each

5 allowed, ≤1 mm each

Contamination by high intensity

light

None


Notes:

 * Defects limits apply to entire wafer surface except for the edge exclusion area.

# Defects shall be existed in the edge area, only defect beyond of the prescribed scope could be considered as reject cause. & the scratches should be checked on Si face only.



4 inch diameter Silicon Carbide (SiC) Substrate Specification

Grade

Zero MPD

Production

Research Grade

Dummy Grade

Diameter100.0 mm±0.5 mm
Thickness4H-N350 μm±25μm
4H-SI500 μm±25μm
Wafer OrientationOff axis : 4.0° toward(112-0) ±0.5° for 4H-N
On axis :<0001>±0.5°°for 4H- SI
Micropipe Density≤1 cm-2≤5 cm-2≤15 cm-2≤50 cm-2
Resistivity4H-N0.015~0.028 Ω·cm
6H-N0.02~0.1 Ω·cm(90%) >1E5 Ω·cm
4/6H-SI>1E5 Ω·cm
Primary Flat{10-10}±5.0°
Primary Flat Length32.5 mm±2.0 mm
Secondary Flat Length18.0 mm±2.0mm
Secondary Flat OrientationSilicon face up: 90° CW. from Prime flat ±5.0°
Edge exclusion3 mm
TTV/Bow /Warp≤15μm /≤25μm /≤40μm
RoughnessPolish   Ra≤1 nm
CMP    Ra≤0.5 nm

Cracks by high 

intensity light

None1 allowed, ≤2 mm

Cumulative length≤10mm, 

single length≤2mm

Hex Plates by high 

intensity light

Cumulative area≤1 %

Cumulative 

a≤1 %

Cumulative 

area3 %

Poly type Areas by high

intensity light

None

Cumulative

 area≤2%

Cumulative 

area≤5%

Scratches by high 

intensity light

3 scratches to 

1×wafer diameter

cumulative length

5 scratches to

1×wafer diameter

cumulative length

5 scratches to 

1×wafer diameter

cumulative length

Edge chipNone

3 allowed, 

≤0.5mm each

5 allowed, 

≤1 mm each

Contamination by 

high intensity light

None


Notes:

* Defects limits apply to entire wafer surface except for the edge exclusion area.

# Defects shall be existed in the edge area, only defect beyond of the prescribed scope could be considered as reject cause. & the scratches should be checked on Si face only.